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ICCAD
2005
IEEE
93views Hardware» more  ICCAD 2005»
14 years 5 months ago
Eliminating wire crossings for molecular quantum-dot cellular automata implementation
— When exploring computing elements made from technologies other than CMOS, it is imperative to investigate the effects of physical implementation constraints. This paper focuses...
Amitabh Chaudhary, Danny Z. Chen, Kevin Whitton, M...
ISCAS
2006
IEEE
148views Hardware» more  ISCAS 2006»
14 years 2 months ago
DF-DICE: a scalable solution for soft error tolerant circuit design
—The Delay Filtered Dual Interlocked storage Cell (DF-DICE) offers a scalable solution in different radiation environments for soft error mitigation. The area and speed performan...
Riaz Naseer, Jeff Draper
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 2 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
14 years 1 months ago
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity ...
Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Ji...
ISMVL
1997
IEEE
134views Hardware» more  ISMVL 1997»
14 years 1 months ago
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams
In this paper, the minimization of incompletely specified multi-valued functions using functional decomposition is discussed. From the aspect of machine learning, learning sample...
Craig M. Files, Rolf Drechsler, Marek A. Perkowski