75 search results - page 4 / 15 » Modeling Crosstalk Induced Delay |
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates th...
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
ASPDAC
2006
ACM
14 years 26 days ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
ISQED
2005
IEEE
14 years 14 days ago
2005
IEEE
Abstract— To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, stagg...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...