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» Modeling Hard-Disk Power Consumption
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ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
14 years 2 months ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
14 years 1 months ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
ISPASS
2010
IEEE
14 years 3 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
ISCC
2008
IEEE
123views Communications» more  ISCC 2008»
14 years 3 months ago
Improving reliability and energy efficiency of disk systems via utilization control
As disk drives become increasingly sophisticated and processing power increases, one of the most critical issues of designing modern disk systems is data reliability. Although num...
Kiranmai Bellam, Adam Manzanares, Xiaojun Ruan, Xi...
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
14 years 3 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li