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» Modeling and evaluation of hardware software designs
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IEEEPACT
2007
IEEE
14 years 1 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
14 years 1 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
CF
2007
ACM
13 years 11 months ago
An analysis of the effects of miss clustering on the cost of a cache miss
In this paper we describe a new technique, called pipeline spectroscopy, and use it to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogra...
Thomas R. Puzak, Allan Hartstein, Philip G. Emma, ...
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
14 years 1 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 11 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah