6229 search results - page 16 / 1246 » Models of Computation for Networks on Chip |
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
CIMCA
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes an innovative work for nanorobot design and manufacturing, using a computer simulation and system on chip prototyping approach. The use of CMOS as integrated ...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating in parallel. The results from PEs n...