Sciweavers

77 search results - page 8 / 16
» Modifying Min-Cut for Hardware and Software Functional Parti...
Sort
View
ISCAS
1999
IEEE
105views Hardware» more  ISCAS 1999»
13 years 11 months ago
Configuration self-test in FPGA-based reconfigurable systems
An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for...
W. Quddus, Abhijit Jas, Nur A. Touba
ICCAD
2007
IEEE
113views Hardware» more  ICCAD 2007»
14 years 1 months ago
The FAST methodology for high-speed SoC/computer simulation
— This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs,...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...
ISLPED
2007
ACM
84views Hardware» more  ISLPED 2007»
13 years 9 months ago
Towards a software approach to mitigate voltage emergencies
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. One a...
Meeta Sharma Gupta, Krishna K. Rangan, Michael D. ...
DATE
2002
IEEE
117views Hardware» more  DATE 2002»
14 years 9 days ago
Effective Software Self-Test Methodology for Processor Cores
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning tech...
Nektarios Kranitis, Antonis M. Paschalis, Dimitris...
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
14 years 8 days ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha