10 search results - page 2 / 2 » Modular Synthesis of Timed Circuits using Partial Order Redu... |
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
In this paper, we present a reduced order inodeling methodology, based on the utilization of optimal non-uniform grids generated by Gaussian spectral rules, for the direct passive...
FPGA
1999
ACM
13 years 11 months ago
1999
ACM
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...