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» Modularity Analysis of Logical Design Models
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DAC
2006
ACM
14 years 8 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
VTS
2005
IEEE
116views Hardware» more  VTS 2005»
14 years 1 months ago
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
Kartik Mohanram
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 4 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
KCAP
2003
ACM
14 years 24 days ago
Modularisation of domain ontologies implemented in description logics and related formalisms including OWL
Modularity is a key requirement for large ontologies in order to achieve re-use, maintainability, and evolution. Mechanisms for ‘normalisation’ to achieve analogous aims are s...
Alan L. Rector
CODES
2003
IEEE
14 years 25 days ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...