A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Modularity is a key requirement for large ontologies in order to achieve re-use, maintainability, and evolution. Mechanisms for ‘normalisation’ to achieve analogous aims are s...
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...