Logic synthesis has made impressive progress in the last decade and has pervaded digital design replacing almost universally manual techniques. A remarkable exception is computer ...
Abstract. We present a systematic procedure for the synthesis and minimisation of digital circuits using propositional satisfiability. We encode the truth table into a canonical s...
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. ...
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...