395 search results - page 15 / 79 » Multilevel Circuit Partitioning |
104
Voted
ICCAD
1994
IEEE
15 years 6 months ago
1994
IEEE
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
115
Voted
ICCAD
2006
IEEE
15 years 11 months ago
2006
IEEE
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
87
Voted
DATE
2000
IEEE
15 years 7 months ago
2000
IEEE
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
107
Voted
ASPDAC
2004
ACM
15 years 8 months ago
2004
ACM
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
132
Voted
ICCAD
1996
IEEE
15 years 6 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...