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ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
14 years 21 hour ago
Storageless Value Prediction Using Prior Register Values
This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce th...
Dean M. Tullsen, John S. Seng
FPL
2010
Springer
111views Hardware» more  FPL 2010»
13 years 5 months ago
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
Abstract--Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rel...
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebe...
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
14 years 1 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
SBACPAD
2005
IEEE
139views Hardware» more  SBACPAD 2005»
14 years 1 months ago
Chained In-Order/Out-of-Order DoubleCore Architecture
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
Miquel Pericàs, Adrián Cristal, Rube...
TVLSI
2010
13 years 2 months ago
A Low-Power DSP for Wireless Communications
This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture--Signal processi...
Hyunseok Lee, Chaitali Chakrabarti, Trevor N. Mudg...