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ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
14 years 1 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...
PC
2007
161views Management» more  PC 2007»
13 years 7 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
CODES
2007
IEEE
14 years 2 months ago
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luc...
BMCBI
2006
123views more  BMCBI 2006»
13 years 7 months ago
SBEAMS-Microarray: database software supporting genomic expression analyses for systems biology
Background: The biological information in genomic expression data can be understood, and computationally extracted, in the context of systems of interacting molecules. The automat...
Bruz Marzolf, Eric W. Deutsch, Patrick Moss, David...
CODES
2003
IEEE
14 years 1 months ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan