6 search results - page 1 / 2 » New Self-Checking Booth Multipliers |
AMCS
2008
13 years 7 months ago
2008
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a...
SBCCI
2003
ACM
14 years 21 days ago
2003
ACM
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
ARITH
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
ISSS
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...