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DATE
2006
IEEE
75views Hardware» more  DATE 2006»
14 years 4 months ago
GALS networks on chip: a new solution for asynchronous delay-insensitive links
In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtai...
G. Campobello, M. Castano, C. Ciofi, Daniele Manga...
ICCAD
1999
IEEE
77views Hardware» more  ICCAD 1999»
14 years 3 months ago
Synthesis for multiple input wires replacement of a gate for wiring consideration
The alternative wire technique attempts to replace a target wire by another wire without changing the logic functionality. In this paper, we propose two new transformations of rep...
Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 4 months ago
A New System Design Methodology for Wire Pipelined SoC
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
Mario R. Casu, Luca Macchiarulo
DAGM
2009
Springer
13 years 8 months ago
HMM-Based Defect Localization in Wire Ropes - A New Approach to Unusual Subsequence Recognition
Abstract. Automatic visual inspection has become an important application of pattern recognition, as it supports the human in this demanding and often dangerous work. Nevertheless,...
Esther-Sabrina Platzer, Josef Nägele, Karl-He...