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ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
14 years 6 months ago
Double-gate SOI devices for low-power and high-performance applications
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...
Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhop...
ICCAD
2008
IEEE
115views Hardware» more  ICCAD 2008»
14 years 6 months ago
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...
Mohammad Ghasemazar, Massoud Pedram
JCP
2007
153views more  JCP 2007»
13 years 9 months ago
An Integrated Educational Platform Implementing Real, Remote Lab-Experiments for Electrical Engineering Courses
—This paper describes an Internet-based laboratory, named Remote Monitored and Controlled Laboratory (RMCLab) developed at University of Patras, Greece, for electrical engineerin...
Dimitris Karadimas, Kostas Efstathiou
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
14 years 3 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
DATE
2009
IEEE
93views Hardware» more  DATE 2009»
14 years 4 months ago
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Ha...