980 search results - page 15 / 196 » Novel Test Pattern Generators for Pseudo-Exhaustive Testing |
ITC
1991
IEEE
14 years 21 days ago
1991
IEEE
Two approaches have been used to balance the cost of generating e ective tests for ICs and the need to increase the ICs' quality level. The rst approach favorsusing high-leve...
CP
1998
Springer
14 years 1 months ago
1998
Springer
In a faulty digital circuit, many (single) faulty gates may explain the observed findings. In this paper we are mostly concerned, not in obtaining alternative diagnoses, but rathe...
EVOW
1999
Springer
14 years 1 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
ICCAD
2002
IEEE
14 years 6 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
EURODAC
1990
IEEE
14 years 1 months ago
1990
IEEE
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...