980 search results - page 25 / 196 » Novel Test Pattern Generators for Pseudo-Exhaustive Testing |
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
DSD
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns have greater ability to detect un-modeled defects. The propose...
ITC
2003
IEEE
14 years 2 months ago
2003
IEEE
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...