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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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ISQED
2010
IEEE
121views Hardware» more  ISQED 2010»
14 years 2 months ago
A novel two-dimensional scan-control scheme for test-cost reduction
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
Chia-Yi Lin, Hung-Ming Chen
EVOW
2001
Springer
14 years 1 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 2 months ago
Impact of Multiple-Detect Test Patterns on Product Quality
This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizi...
Brady Benware, Chris Schuermyer, Sreenevasan Ranga...
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
14 years 1 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
14 years 1 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...