Sciweavers

799 search results - page 19 / 160
» On Failures and Faults
Sort
View
DATE
2009
IEEE
94views Hardware» more  DATE 2009»
14 years 2 months ago
Improving compressed test pattern generation for multiple scan chain failure diagnosis
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the e...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
DATE
2006
IEEE
99views Hardware» more  DATE 2006»
14 years 1 months ago
Multiple-fault diagnosis based on single-fault activation and single-output observation
In this paper, we propose a new circuit transformation technique in conjunction with the use of a special diagnostic test pattern, named SO-SLAT pattern, to achieve higher multipl...
Yung-Chieh Lin, Kwang-Ting Cheng
GLVLSI
2005
IEEE
83views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Diagnosing multiple transition faults in the absence of timing information
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...
Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Ven...
ITC
2000
IEEE
93views Hardware» more  ITC 2000»
13 years 12 months ago
Stuck-fault tests vs. actual defects
This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and comp...
Edward J. McCluskey, Chao-Wen Tseng
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 11 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...