53 search results - page 5 / 11 » On Minimization of Peak Power for Scan Circuit during Test |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
ISLPED
2003
ACM
14 years 21 days ago
2003
ACM
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
EVOW
1999
Springer
13 years 11 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...