1187 search results - page 6 / 238 » On Modeling Cross-Talk Faults |
ASPDAC
2009
ACM
14 years 3 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
ITC
1996
IEEE
14 years 22 days ago
1996
IEEE
common use is the distinction into two (abstract) fault models: A new fault modelling scheme for integrated analogue general the "Single Hard Fault Model (SHFM)" and the ...
VTS
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establi...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
DFT
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly de...