305 search results - page 59 / 61 » On modeling top-down VLSI design |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
SAMOS
2004
Springer
14 years 24 days ago
2004
Springer
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...