166 search results - page 16 / 34 » On testing delay faults in macro-based combinational circuit... |
GLVLSI
1999
IEEE
14 years 3 days ago
1999
IEEE
This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...
VTS
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
DSD
2007
IEEE
14 years 2 months ago
2007
IEEE
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
ICCAD
1997
IEEE
14 years 9 hour ago
1997
IEEE
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational ...
ATS
2003
IEEE
14 years 1 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...