372 search results - page 15 / 75 » On the Fault Testing for Reversible Circuits |
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible lo...
ASPDAC
1998
ACM
14 years 25 days ago
1998
ACM
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
EURODAC
1995
IEEE
14 years 4 days ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such ...
GLVLSI
1999
IEEE
14 years 27 days ago
1999
IEEE
This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...