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» On the Fault Testing for Reversible Circuits
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TODAES
1998
64views more  TODAES 1998»
13 years 8 months ago
Functional test generation for delay faults in combinational circuits
Irith Pomeranz, Sudhakar M. Reddy
DFT
2003
IEEE
114views VLSI» more  DFT 2003»
14 years 1 months ago
CodSim -- A Combined Delay Fault Simulator
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...
DATE
2005
IEEE
122views Hardware» more  DATE 2005»
14 years 2 months ago
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...
Raja K. K. R. Sandireddy, Vishwani D. Agrawal
DFT
2006
IEEE
148views VLSI» more  DFT 2006»
13 years 10 months ago
Bilateral Testing of Nano-scale Fault-tolerant Circuits
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
Lei Fang, Michael S. Hsiao
FTCS
1993
94views more  FTCS 1993»
13 years 10 months ago
Balance Testing of Logic Circuits
We present a new test response compression method called cumulative balance testing (CBT)that extends both balance testing and accumulatorcompression testing. CBT uses an accumulat...
Krishnendu Chakrabarty, John P. Hayes