Sciweavers

372 search results - page 26 / 75
» On the Fault Testing for Reversible Circuits
Sort
View
ICCAD
2001
IEEE
84views Hardware» more  ICCAD 2001»
14 years 5 months ago
On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits
Given a test set for stuck-at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don’...
Seiji Kajihara, Kohei Miyase
ETS
2009
IEEE
79views Hardware» more  ETS 2009»
13 years 6 months ago
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
Michael A. Kochte, Christian G. Zoellin, Hans-Joac...
FDTC
2010
Springer
124views Cryptology» more  FDTC 2010»
13 years 6 months ago
Optical Fault Masking Attacks
This paper introduces some new types of optical fault attacks called fault masking attacks. These attacks are aimed at disrupting of the normal memory operation through preventing ...
Sergei Skorobogatov
DATE
1998
IEEE
92views Hardware» more  DATE 1998»
14 years 26 days ago
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis...
DATE
1997
IEEE
109views Hardware» more  DATE 1997»
14 years 5 days ago
Sequential circuit test generation using dynamic state traversal
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...