372 search results - page 53 / 75 » On the Fault Testing for Reversible Circuits |
TCAD
2002
13 years 7 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback p...
ATS
2003
IEEE
14 years 24 days ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...