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PODC
2011
ACM
13 years 23 days ago
On the power of hardware transactional memory to simplify memory management
Dynamic memory management is a significant source of complexity in the design and implementation of practical concurrent data structures. We study how hardware transactional memo...
Aleksandar Dragojevic, Maurice Herlihy, Yossi Lev,...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 10 months ago
High-Performance Power Grids For Nanometer Technologies
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
Sachin S. Sapatnekar
HIPC
2003
Springer
14 years 3 months ago
Power-Aware Adaptive Issue Queue and Register File
In this paper, we present a novel technique to reduce dynamic and static power dissipation in the issue queue. The proposed scheme is based on delaying the dispatch of instructions...
Jaume Abella, Antonio González
DAC
2009
ACM
14 years 11 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
DAC
1999
ACM
14 years 2 months ago
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
Priyadarshan Patra, Unni Narayanan