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    » On the energy-efficiency of speculative hardware
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    DATE
    2005
    IEEE
    123views Hardware» more  DATE 2005»
    An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor
    14 years 1 months ago
    An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor
    Download  www.date-conference.com
    Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo
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    ASPDAC
    2009
    ACM
    112views Hardware» more  ASPDAC 2009»
    Compiler-managed register file protection for energy-efficient soft error reduction
    13 years 11 months ago
    Compiler-managed register file protection for energy-efficient soft error reduction
    Download  www.public.asu.edu
    Abstract-- For embedded systems where neither energy nor reliability can be easily sacrificed, we present an energy efficient soft error protection scheme for register files (RF). ...
    Jongeun Lee, Aviral Shrivastava
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    IEEEPACT
    2009
    IEEE
    166views Distributed And Parallel Com...» more  IEEEPACT 2009»
    Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
    14 years 2 months ago
    Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
    Download  cseweb.ucsd.edu
    — This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
    Leo Porter, Bumyong Choi, Dean M. Tullsen
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    AICCSA
    2007
    IEEE
    78views Hardware» more  AICCSA 2007»
    WSNodeRater - An Optimized Reputation System Framework for Security Aware Energy Efficient Geographic Routing in WSNs
    14 years 1 months ago
    WSNodeRater - An Optimized Reputation System Framework for Security Aware Energy Efficient Geographic Routing in WSNs
    Download  isi.kfupm.edu.sa
    Ismat K. Maarouf, A. R. Naseer
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    ASPDAC
    2004
    ACM
    94views Hardware» more  ASPDAC 2004»
    Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
    14 years 1 months ago
    Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
    Download  www.ics.uci.edu
    Aviral Shrivastava, Nikil D. Dutt
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