Sciweavers

415 search results - page 50 / 83
» On the energy-efficiency of speculative hardware
Sort
View
ISCA
2012
IEEE
270views Hardware» more  ISCA 2012»
11 years 11 months ago
Revisiting hardware-assisted page walks for virtualized systems
Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current twodimensional (2...
Jeongseob Ahn, Seongwook Jin, Jaehyuk Huh
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
14 years 2 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ICCAD
2005
IEEE
105views Hardware» more  ICCAD 2005»
14 years 5 months ago
Weighted control scheduling
Abstract — This paper describes a practical technique for the optimal scheduling of control dominated systems minimizing the weighted average latency over all control branches. S...
Aravind Vijayakumar, Forrest Brewer
DATE
2007
IEEE
93views Hardware» more  DATE 2007»
14 years 3 months ago
Testing in the year 2020
Testing today of a several hundred million transistor System-on-Chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What will test technology be...
Rajesh Galivanche, Rohit Kapur, Antonio Rubio
MICRO
1999
IEEE
136views Hardware» more  MICRO 1999»
14 years 1 months ago
Read-After-Read Memory Dependence Prediction
: We identify that typical programs exhibit highly regular read-after-read (RAR) memory dependence streams. We exploit this regularity by introducing read-after-read (RAR) memory d...
Andreas Moshovos, Gurindar S. Sohi