Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current twodimensional (2...
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Abstract — This paper describes a practical technique for the optimal scheduling of control dominated systems minimizing the weighted average latency over all control branches. S...
Testing today of a several hundred million transistor System-on-Chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What will test technology be...
: We identify that typical programs exhibit highly regular read-after-read (RAR) memory dependence streams. We exploit this regularity by introducing read-after-read (RAR) memory d...