415 search results - page 54 / 83 » On the energy-efficiency of speculative hardware |
FPL
2007
Springer
14 years 1 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...