261 search results - page 32 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
108
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COR
2008
15 years 2 months ago
2008
-- The optimal buffer allocation in queueing network systems is a difficult stochastic, non-linear, integer mathematical programming problem. Moreover, the objective function, the ...
126
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ICCAD
2001
IEEE
15 years 11 months ago
2001
IEEE
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
106
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ICCAD
1997
IEEE
15 years 6 months ago
1997
IEEE
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
107
Voted
ISMVL
2007
IEEE
15 years 9 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
137
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VLDB
2002
ACM
15 years 2 months ago
2002
ACM
Accurate prediction of operator execution time is a prerequisite for database query optimization. Although extensively studied for conventional disk-based DBMSs, cost modeling in ...