261 search results - page 9 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ATS
2000
IEEE
13 years 12 months ago
2000
IEEE
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
ETS
2009
IEEE
13 years 5 months ago
2009
IEEE
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
VTS
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
DDECS
2006
IEEE
14 years 1 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
MTDT
2000
IEEE
13 years 12 months ago
2000
IEEE
In this work, we present the application of Generalized Linear Feedback Shift Registers (GLFSRs) for generation of patterns for pseudo-random memory Built-In SelfTest (BIST). Rece...