38 search results - page 6 / 8 » Optimal Transistor Tapering for High-Speed CMOS Circuits |
VLSID
1999
IEEE
14 years 25 days ago
1999
IEEE
A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the rst order behavior of a MOS transistor in the saturation regi...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...