19 search results - page 4 / 4 » Optimal non-uniform wire-sizing under the Elmore delay model |
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...
ICCAD
2001
IEEE
14 years 7 months ago
2001
IEEE
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
DATE
2002
IEEE
14 years 3 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
ASPDAC
2001
ACM
14 years 2 months ago
2001
ACM
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...