Sciweavers

38 search results - page 6 / 8
» Optimal topology exploration for application-specific 3D arc...
Sort
View
IPPS
2007
IEEE
14 years 1 months ago
Towards Optimal Multi-level Tiling for Stencil Computations
Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many til...
Lakshminarayanan Renganarayanan, Manjukumar Harthi...
ARITH
2007
IEEE
13 years 11 months ago
Robust Energy-Efficient Adder Topologies
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...
Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, R...
DAC
2006
ACM
14 years 8 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
14 years 1 months ago
Top-down heterogeneous synthesis of analog and mixed-signal systems
A new approach for automated synthesis of analog and mixed-signal systems is presented. The heterogeneous genetic optimization strategy starts from a functional description and ev...
Ewout Martens, Georges G. E. Gielen
PEWASUN
2005
ACM
14 years 1 months ago
Three-dimensional routing in underwater acoustic sensor networks
Underwater sensor networks will find applications in oceanographic data collection, pollution monitoring, offshore exploration, disaster prevention, assisted navigation, and tact...
Dario Pompili, Tommaso Melodia