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DATE
2007
IEEE
107views Hardware» more  DATE 2007»
14 years 1 months ago
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
K. Van Renterghem, P. Demuytere, Dieter Verhulst, ...
DAC
1999
ACM
14 years 8 months ago
Power Efficient Mediaprocessors: Design Space Exploration
We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a catego...
Johnson Kin, Chunho Lee, William H. Mangione-Smith...
CODES
2005
IEEE
14 years 1 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
ICCAD
2003
IEEE
142views Hardware» more  ICCAD 2003»
14 years 4 months ago
Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning
Transmitting compressed data can reduce inter-processor communication traffic and create new opportunities for DVS (dynamic voltage scaling) in distributed embedded systems. Howe...
Jinfeng Liu, Pai H. Chou
CODES
2007
IEEE
14 years 1 months ago
HySim: a fast simulation framework for embedded software development
Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology,...
Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leu...