70 search results - page 7 / 14 » Optimization of combinational and sequential logic circuits ... |
DATE
2000
IEEE
14 years 29 days ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
ICCAD
1999
IEEE
14 years 26 days ago
1999
IEEE
A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay . We describe a new delay optimi...
ISLPED
2004
ACM
14 years 2 months ago
2004
ACM
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
ISCAS
2002
IEEE
14 years 1 months ago
2002
IEEE
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...