72 search results - page 9 / 15 » Optimization techniques for high-performance digital circuit... |
TCAD
1998
13 years 7 months ago
1998
—This paper introduces a novel optimization paradigm for increasing the throughput of digital systems. The basic idea consists of transforming fixed-latency units into variable-...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...