155 search results - page 13 / 31 » Optimizations for a Highly Cost-Efficient Programmable Logic... |
ISQED
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— Self-calibrating designs have recently gained momentum as an alternative to methods relying on worst-case characterisation of silicon [2], [4], [8]. So far, reliable op...
FCCM
2008
IEEE
14 years 2 months ago
2008
IEEE
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
HIPC
2009
Springer
13 years 6 months ago
2009
Springer
Abstract--With General Purpose programmable GPUs becoming more and more popular, automated tools are needed to bridge the gap between achievable performance from highly parallel ar...
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in h...