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» Optimizing Loop Performance for Clustered VLIW Architectures
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MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
14 years 1 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
VLSID
2006
IEEE
160views VLSI» more  VLSID 2006»
14 years 8 months ago
An Approach to Architectural Enhancement for Embedded Speech Applications
Advances in Human Computer Interaction(HCI) technology has resulted in widespread development of natural language and speech applications. These applications are known to be compu...
Soumyajit Dey, Susmit Biswas, Arijit Mukhopadhyay,...
ASPDAC
2000
ACM
109views Hardware» more  ASPDAC 2000»
13 years 11 months ago
A technique for QoS-based system partitioning
Quality of service (QoS) has been an important topic of many research communities. Combined with an advanced and retargetable compiler, variability of applicationsspecific very lar...
Johnson S. Kin, Chunho Lee, William H. Mangione-Sm...
VLSISP
2008
159views more  VLSISP 2008»
13 years 7 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
14 years 21 days ago
A Video Compression Case Study on a Reconfigurable VLIW Architecture
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
Davide Rizzo, Osvaldo Colavin