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GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
ICC
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract—We propose chip waveforms for essentially fullresponse signaling in DS-CDMA systems that employ offset quadrature modulation formats. The waveforms are optimal in the se...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
ICCAD
1997
IEEE
14 years 13 days ago
1997
IEEE
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In...
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...