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» Optimizing pipelines for power and performance
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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
14 years 1 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
CHES
2003
Springer
100views Cryptology» more  CHES 2003»
14 years 1 months ago
Multi-channel Attacks
We introduce multi-channel attacks, i.e., side-channel attacks which utilize multiple side-channels such as power and EM simultaneously. We propose an adversarial model which combi...
Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
14 years 27 days ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
14 years 20 days ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
ISLPED
2000
ACM
77views Hardware» more  ISLPED 2000»
14 years 11 days ago
A recursive algorithm for low-power memory partitioning
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
Luca Benini, Alberto Macii, Massimo Poncino