2048 search results - page 8 / 410 » Optimizing pipelines for power and performance |
ISCA
2005
IEEE
14 years 3 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
ICCAD
2008
IEEE
14 years 7 months ago
2008
IEEE
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
ISLPED
2005
ACM
14 years 3 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
FCCM
2005
IEEE
14 years 3 months ago
2005
IEEE
FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability t...
VLSID
2006
IEEE
14 years 10 months ago
2006
IEEE
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...