954 search results - page 22 / 191 » Optimizing power and performance for reliable on-chip networ... |
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
ICS
2003
Tsinghua U.
14 years 29 days ago
2003
Tsinghua U.
Power consumption is a critical issue in interconnection network design, driven by power-related design constraints, such as thermal and power delivery design. Usually, off-line w...