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ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
14 years 2 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
ICCAD
1999
IEEE
120views Hardware» more  ICCAD 1999»
14 years 2 months ago
Regularity extraction via clan-based structural circuit decomposition
Identifying repeating structural regularities in circuits allows the minimization of synthesis, optimization, and layout e orts. We introduce in this paper a novel method for ident...
Soha Hassoun, Carolyn McCreary
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
14 years 2 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
ASPDAC
1998
ACM
105views Hardware» more  ASPDAC 1998»
14 years 2 months ago
Techniques for Functional Test Pattern Execution
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
Inki Hong, Miodrag Potkonjak
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
14 years 2 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...