339 search results - page 31 / 68 » Overview on Low Power SoC Design Technology |
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— Thermal characterization of ICs and on-chip temperature monitoring has become a key task in electronic engineering. In this paper, we present the design of an on-chip C...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
— The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footpr...
ISLPED
2009
ACM
14 years 7 days ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...