339 search results - page 36 / 68 » Overview on Low Power SoC Design Technology |
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
ISCA
2006
IEEE
13 years 7 months ago
2006
IEEE
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
PATMOS
2004
Springer
14 years 27 days ago
2004
Springer
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
ACISP
2000
Springer
13 years 12 months ago
2000
Springer
We present a new identification scheme which is based on Legendre symbols modulo a certain hidden prime and which is naturally suited for low power, low memory applications. 1 Ove...
ISLPED
2003
ACM
14 years 24 days ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...