Abstract--Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requiremen...
Abstract-- In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending...
Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu ...
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
: Most of the recently discussed and commercially introduced test stimulus data compression techniques are based on low care bit densities found in typical scan test vectors. Data ...
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many po...