360 search results - page 43 / 72 » Parallel processing flow models on desktop hardware |
SASP
2009
IEEE
14 years 3 months ago
2009
IEEE
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
ICCD
2007
IEEE
14 years 15 days ago
2007
IEEE
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
HPCA
1998
IEEE
14 years 27 days ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
ICCAD
1994
IEEE
14 years 23 days ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...